1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
2. Related Art
Conventional methods for manufacturing an embedded polysilicon layer typically includes a method described in, for example, Japanese Patent Laid-Open No. H06-314,739 (1994). The method for manufacturing the polysilicon layer described in Japanese Patent Laid-Open No. H06-314,739 is shown in FIGS. 6A to 6C and FIGS. 7D to 7F.
First of all, a trench 113 is formed in a silicon substrate 110. Thereafter, a p-type diffusion layer (not shown) and an n-type diffusion layer (not shown) are formed in predetermined locations of the silicon substrate 110. Then, a silicon oxide film 112 is formed on surfaces of a silicon substrate 110 that includes an interior wall of a trench 113 via a thermal oxidation process (FIG. 6A).
Subsequently, a polysilicon film 114 is formed on the surface of the silicon oxide film 112 via a chemical vapor deposition (CVD) process. The polysilicon film 114 is formed so as to plug the trench 113 and to cover the entire surface of the silicon oxide film 112. A dip 114a is formed in a position located above the trench 113 in an upper surface of the polysilicon film 114 (FIG. 6B). Next, a silicon nitride film 116 is formed to cover the entire surface of the polysilicon film 114 via the CVD process (FIG. 6C).
Then, the silicon nitride film 116 is etched. As a result, the silicon nitride film 116a partially remains only in the dip 114a (FIG. 7D). Next, the a top surface of the polysilicon film 114 is oxidized, and further, the formed oxide-film (not shown) is removed. In this case, a phenomenon that an oxidization of the polysilicon film 114 does not proceed from the silicon nitride film 116a remained in the dip 114a is utilized, so that the depth of the dip 114a is reduced to planarize the polysilicon film 114 (FIG. 7E). Then, the polysilicon film 114 is etched to form an embedded polysilicon layer 115 in the trench 113 (FIG. 7F).
However, in the conventional technology described in Japanese Patent Laid-Open No. H06-314739, the additional process for forming the embedded polysilicon layer 115 causes a very complicated situation. More specifically, the following processes are required for planarizing the surface of the embedded polysilicon layer 115 formed in the trench 113:
a silicon nitride film 116 is formed on the polysilicon film 114 (FIG. 6C), and further, the silicon nitride film 116 is etched (FIG. 7D), and thereafter, an oxidization of the polysilicon film 114 is progressed until the oxidization is reached to a specified location (i.e., bottom of dip 114a). Further, since the p-type diffusion layer (not shown) and the n-type diffusion layer (not shown) are formed in the silicon substrate 110, a countermeasure for a prevention from an oxidization of the silicon substrate 110 should be taken. More specifically, a countermeasure for a prevention from an oxidization of the silicon substrate 110 is described in example 2 of Japanese Patent Laid-Open No. H06-314,739, in which a silicon nitride film is provided as an etch stop film in the polysilicon film 114 to prevent the oxidization of the silicon substrate 110. As such, the process for forming the embedded polysilicon layer 115 causes very complicated situation, and further, it is very difficult to appropriately control a geometry of the embedded polysilicon layer 115. In addition, it is also difficult to achieve a sufficient planarization of the surface of the embedded polysilicon layer 115, and thus concave and convex portions are still remained in the surface. Therefore, a problem is occurred, when the embedded polysilicon layer 115 is employed for the device isolation layer, an interconnect formed on the surface of the embedded polysilicon layer 115 is easily be broken.
On the contrary, when a method other than the method described in Japanese Patent Laid-Open No. H06-314739 is employed to form the embedded polysilicon layer 115 as the polysilicon gate electrode, threshold voltage of a transistor may fluctuate. Problems occurred when methods for manufacturing the device other than the above-described method will be described as follows, in reference to FIGS. 4A to 4C and FIGS. 5D and SE.
First of all, a trench 113 is formed in a silicon substrate 110 via an exposure technology and an etching technology. Then, a silicon oxide film is formed onto an interior wall of the trench 113 via a thermal oxidation process or the like. This provides a silicon oxide film 112 formed on the surface of the silicon substrate 110 including the interior wall of the trench 113 (FIG. 4A). Subsequently, a polysilicon film 114 is formed on the surface of the silicon oxide film 112 via a CVD process. The polysilicon film 114 is formed so as to plug the trench 113 and to cover the entire surface of the silicon oxide film 112 (FIG. 4B).
Then, the polysilicon film 114 on the silicon oxide film 112 is etched back to be removed therefrom. Such etching back process provides an embedded polysilicon layer 115 formed in the trench 113. In this case, an excessive etching (i.e., over etching) may be required for compensating a positional variation in the levels (heights) of surface in the silicon substrate 110 and/or a difference in etching rates. Therefore, a surface of the embedded polysilicon layer 115 may often be isolated from the surface of the silicon substrate 110 in the trench 113, resulting in partially exposing an interior wall 113a of the trench 113 (FIG. 4C).
Then, an n-type impurity is doped into the silicon substrate 110 through a mask of the embedded polysilicon layer 115 and the silicon oxide film 112, which are formed in the trench 113 (FIG. 5D). This provides a pair of n-type diffusion layers 118 formed in surface regions of the silicon substrate 110 located aside of the trench 113, and additionally, unwanted doping with the impurity is simultaneously carried out from the interior wall 113a of the trench 113. This provides an anomalous diffusion region 118a formed in the n-type diffusion layer 118, which is formed to have larger dimension than the planned dimension for forming the n-type diffusion layer 118 (FIG. 5E). Therefore, a fluctuation in threshold voltage of the transistor is increased, leading to a deterioration in electrical characteristics of the semiconductor device.
As described above, it is very difficult to precisely control the geometry of the polysilicon gate electrode 115, when the embedded polysilicon layer (polysilicon gate electrode) 115 is formed in the trench 113. Therefore, a novel process is required, which allows forming a polysilicon gate electrode with a simple and easy process, and which allows providing a semiconductor device having stable electrical characteristics provided by stabilizing a threshold voltage of a transistor.